Japanese Patent Application Publication No. 2008-135522 (hereinbelow referred to as Patent Literature 1) discloses a semiconductor device including a cell region in which a MOS structure is provided, and a circumferential region on a periphery of the cell region. A plurality of trenches is provided in the circumferential region so as to circumscribe the cell region, and an insulating layer is filled in each trench. A p-type bottom-surface surrounding region is provided at a lower end of each trench in the circumferential region. When a MOSFET is turned off, a depletion layer extends from the cell region to the circumferential region. At this occasion, the respective bottom-surface surrounding regions enhance the extension of the depletion layer. Due to this, a high voltage resistance can be obtained by this structure.